/*
 * Copyright (c) 2006-2018, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#ifndef __ROCKCHIP_DWMCI_H__
#define __ROCKCHIP_DWMCI_H__

#define DWMCI_CTRL                               0x0000 // W 0x00000000 Control register
#define DWMCI_PWREN                              0x0004 // W 0x00000000 Power-enable register
#define DWMCI_CLKDIV                             0x0008 // W 0x00000000 Clock-divider register
#define DWMCI_CLKSRC                             0x000c // W 0x00000000 SD Clock Source Register
#define DWMCI_CLKENA                             0x0010 // W 0x00000000 Clock-enable register
#define DWMCI_TMOUT                              0x0014 // W 0xffffff40 Time-out register
#define DWMCI_CTYPE                              0x0018 // W 0x00000000 Card-type register
#define DWMCI_BLKSIZ                             0x001c // W 0x00000200 Block-size register
#define DWMCI_BYTCNT                             0x0020 // W 0x00000200 Byte-count register
#define DWMCI_INTMASK                            0x0024 // W 0x00000000 Interrupt-mask register
#define DWMCI_CMDARG                             0x0028 // W 0x00000000 Command-argument register
#define DWMCI_CMD                                0x002c // W 0x00000000 Command register
#define DWMCI_RESP0                              0x0030 // W 0x00000000 Response-0 register
#define DWMCI_RESP1                              0x0034 // W 0x00000000 Response-1 register
#define DWMCI_RESP2                              0x0038 // W 0x00000000 Response-2 register
#define DWMCI_RESP3                              0x003c // W 0x00000000 Response-3 register
#define DWMCI_MINTSTS                            0x0040 // W 0x00000000 Masked interrupt-status register
#define DWMCI_RINTSTS                            0x0044 // W 0x00000000 Raw interrupt-status register
#define DWMCI_STATUS                             0x0048 // W 0x00000406 Status register
#define DWMCI_FIFOTH                             0x004c // W 0x00000000 FIFO threshold register
#define DWMCI_CDETECT                            0x0050 // W 0x00000000 Card-detect register
#define DWMCI_WRTPRT                             0x0054 // W 0x00000000 Write-protect register
#define DWMCI_TCBCNT                             0x005c // W 0x00000000 Transferred CIU card byte count
#define DWMCI_TBBCNT                             0x0060 // W 0x00000000 Transferred host/DMA to/from BIU-FIFO byte count
#define DWMCI_DEBNCE                             0x0064 // W 0x00ffffff Card detect debounce register
#define DWMCI_USRID                              0x0068 // W 0x07967797 User ID register
#define DWMCI_VERID                              0x006c // W 0x5342270a Synopsys version ID register
#define DWMCI_HCON                               0x0070 // W 0x00000000 Hardware configuration register
#define DWMCI_UHS_REG                            0x0074 // W 0x00000000 UHS-1 register
#define DWMCI_RSTN                               0x0078 // W 0x00000001 Hardware reset register
#define DWMCI_BMOD                               0x0080 // W 0x00000000 Bus mode register
#define DWMCI_PLDMND                             0x0084 // W 0x00000000 Poll demand register
#define DWMCI_DBADDR                             0x0088 // W 0x00000000 Descriptor list base address register
#define DWMCI_IDSTS                              0x008c // W 0x00000000 Internal DMAC status register
#define DWMCI_IDINTEN                            0x0090 // W 0x00000000 Internal DMAC interrupt enable register
#define DWMCI_DSCADDR                            0x0094 // W 0x00000000 Current host descriptor address register
#define DWMCI_BUFADDR                            0x0098 // W 0x00000000 Current buffer descriptor address register
#define DWMCI_CARDTHRCTL                         0x0100 // W 0x00000000 Card read threshold enable register
#define DWMCI_BACK_END_POWER                     0x0104 // W 0x00000000 Back-end power register
#define DWMCI_EMMC_DDR_REG                       0x010c // W 0x00000000 eMMC 4.5 ddr start bit detection control register
#define DWMCI_FIFO_BASE                          0x0200 // W 0x00000000 FIFO base address register

/* DWMCI_CTRL */
#define DWMCI_CTRL_USE_INTERNAL_DMAC_SHIFT       (25)
#define DWMCI_CTRL_USE_INTERNAL_DMAC_MASK        (0x1 << DWMCI_CTRL_USE_INTERNAL_DMAC_SHIFT)
#define DWMCI_CTRL_USE_INTERNAL_DMAC             (0x1 << DWMCI_CTRL_USE_INTERNAL_DMAC_SHIFT)
#define DWMCI_CTRL_CEATA_DEV_INT_STATUS_SHIFT    (11)
#define DWMCI_CTRL_CEATA_DEV_INT_STATUS_MASK     (0x1 << DWMCI_CTRL_CEATA_DEV_INT_STATUS_SHIFT)
#define DWMCI_CTRL_SEND_AUTO_STOP_CCSD_SHIFT     (10)
#define DWMCI_CTRL_SEND_AUTO_STOP_CCSD_MASK      (0x1 << DWMCI_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)
#define DWMCI_CTRL_SEND_CCSD_SHIFT               (9)
#define DWMCI_CTRL_SEND_CCSD_MASK                (0x1 << DWMCI_CTRL_SEND_CCSD_SHIFT)
#define DWMCI_CTRL_ABORT_READ_DATA_SHIFT         (8)
#define DWMCI_CTRL_ABORT_READ_DATA_MASK          (0x1 << DWMCI_CTRL_ABORT_READ_DATA_SHIFT)
#define DWMCI_CTRL_SEND_IRQ_RESPONSE_SHIFT       (7)
#define DWMCI_CTRL_SEND_IRQ_RESPONSE_MASK        (0x1 << DWMCI_CTRL_SEND_IRQ_RESPONSE_SHIFT)
#define DWMCI_CTRL_READ_WAIT_SHIFT               (6)
#define DWMCI_CTRL_READ_WAIT_MASK                (0x1 << DWMCI_CTRL_READ_WAIT_SHIFT)
#define DWMCI_CTRL_DMA_ENABLE_SHIFT              (5)
#define DWMCI_CTRL_DMA_ENABLE_MASK               (0x1 << DWMCI_CTRL_DMA_ENABLE_SHIFT)
#define DWMCI_CTRL_DMA_ENABLE                    (0x1 << DWMCI_CTRL_DMA_ENABLE_SHIFT)
#define DWMCI_CTRL_INT_ENABLE_SHIFT              (4)
#define DWMCI_CTRL_INT_ENABLE_MASK               (0x1 << DWMCI_CTRL_INT_ENABLE_SHIFT)
#define DWMCI_CTRL_DMA_RESET_SHIFT               (2)
#define DWMCI_CTRL_DMA_RESET_MASK                (0x1 << DWMCI_CTRL_DMA_RESET_SHIFT)
#define DWMCI_CTRL_DMA_RESET                     (0x1 << DWMCI_CTRL_DMA_RESET_SHIFT)
#define DWMCI_CTRL_FIFO_RESET_SHIFT              (1)
#define DWMCI_CTRL_FIFO_RESET_MASK               (0x1 << DWMCI_CTRL_FIFO_RESET_SHIFT)
#define DWMCI_CTRL_FIFO_RESET                    (0x1 << DWMCI_CTRL_FIFO_RESET_SHIFT)
#define DWMCI_CTRL_RESET_SHIFT                   (0)
#define DWMCI_CTRL_RESET_MASK                    (0x1 << DWMCI_CTRL_RESET_SHIFT)
#define DWMCI_CTRL_RESET                         (0x1 << DWMCI_CTRL_RESET_SHIFT)
#define DWMCI_CTRL_RESET_ALL		             (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET | DWMCI_CTRL_DMA_RESET)

/* DWMCI_PWREN */
#define DWMCI_PWREN_ENABLE_SHIFT                 (0)
#define DWMCI_PWREN_ENABLE_MASK                  (0x1 << DWMCI_PWREN_ENABLE_SHIFT)
#define DWMCI_PWREN_DISABLE                      (0x0 << DWMCI_PWREN_ENABLE_SHIFT)
#define DWMCI_PWREN_ENABLE                       (0x1 << DWMCI_PWREN_ENABLE_SHIFT)

/* DWMCI_CLKDIV */
#define DWMCI_CLKDIV_CLK_DIVIDER0_SHIFT          (0)
#define DWMCI_CLKDIV_CLK_DIVIDER0_MASK           (0xFF << DWMCI_CLKDIV_CLK_DIVIDER0_SHIFT)

/* DWMCI_CLKSRC */
#define DWMCI_CLKDIV_CLK_SOURCE_SHIFT            (0)
#define DWMCI_CLKDIV_CLK_SOURCE_MASK             (0x3 << DWMCI_CLKDIV_CLK_SOURCE_SHIFT)

/* DWMCI_CLKENA */
#define DWMCI_CLKENA_CCLK_LOW_POWER_SHIFT        (16)
#define DWMCI_CLKENA_CCLK_LOW_POWER_MASK         (0x1 << DWMCI_CLKENA_CCLK_LOW_POWER_SHIFT)
#define DWMCI_CLKENA_CCLK_LOW_POWER              (0x1 << DWMCI_CLKENA_CCLK_LOW_POWER_SHIFT)
#define DWMCI_CLKENA_CCLK_ENABLE_SHIFT           (0)
#define DWMCI_CLKENA_CCLK_ENABLE_MASK            (0x1 << DWMCI_CLKENA_CCLK_ENABLE_SHIFT)
#define DWMCI_CLKENA_CCLK_ENABLE                 (0x1 << DWMCI_CLKENA_CCLK_ENABLE_SHIFT)
#define DWMCI_CLKENA_CCLK_DISABLE                (0x0 << DWMCI_CLKENA_CCLK_ENABLE_SHIFT)

/* DWMCI_TMOUT */
#define DWMCI_TMOUT_DATA_TIMEOUT_SHIFT           (8))
#define DWMCI_TMOUT_DATA_TIMEOUT_MASK            (0xFFFFFF << DWMCI_TMOUT_DATA_TIMEOUT_SHIFT)
#define DWMCI_TMOUT_RESPONSE_TIMEOUT_SHIFT       (0)
#define DWMCI_TMOUT_RESPONSE_TIMEOUT_MASK        (0xFF << DWMCI_TMOUT_RESPONSE_TIMEOUT_SHIFT)

/* DWMCI_CTYPE */
#define DWMCI_CTYPE_CARD_WIDTH_8_SHIFT           (16)
#define DWMCI_CTYPE_CARD_WIDTH_8_MASK            (0x1 << DWMCI_CTYPE_CARD_WIDTH_8_SHIFT)
#define DWMCI_CTYPE_CARD_WIDTH_SHIFT             (0)
#define DWMCI_CTYPE_CARD_WIDTH_MASK              (0x1 << DWMCI_CTYPE_CARD_WIDTH_SHIFT)
#define DWMCI_CTYPE_CARD_1BIT                    (0x0 << DWMCI_CTYPE_CARD_WIDTH_SHIFT)
#define DWMCI_CTYPE_CARD_4BIT                    (0x1 << DWMCI_CTYPE_CARD_WIDTH_SHIFT)
#define DWMCI_CTYPE_CARD_8BIT                    (0x1 << DWMCI_CTYPE_CARD_WIDTH_8_SHIFT)

/* DWMCI_BLKSIZ */
#define DWMCI_BLKSIZ_SHIFT                       (0)
#define DWMCI_BLKSIZ_MASK                        (0xFFFF << DWMCI_BLKSIZ_SHIFT)

/* DWMCI_BYTCNT */
#define DWMCI_BYTCNT_SHIFT                       (0)
#define DWMCI_BYTCNT_MASK                        (0xFFFFFFFF << DWMCI_BYTCNT_SHIFT)

/* DWMCI_INTMASK */
#define DWMCI_INTMASK_SDIO_SHIFT                 (24)
#define DWMCI_INTMASK_SDIO_MASK                  (0x1 << DWMCI_INTMASK_SDIO_SHIFT)
#define DWMCI_INTMASK_DATA_NOBUSY_SHIFT          (16)
#define DWMCI_INTMASK_DATA_NOBUSY_MASK           (0x1 << DWMCI_INTMASK_DATA_NOBUSY_SHIFT)
#define DWMCI_INTMASK_EBE_SHIFT                  (15)
#define DWMCI_INTMASK_EBE_MASK                   (0x1 << DWMCI_INTMASK_EBE_SHIFT)
#define DWMCI_INTMASK_ACD_SHIFT                  (14)
#define DWMCI_INTMASK_ACD_MASK                   (0x1 << DWMCI_INTMASK_ACD_SHIFT)
#define DWMCI_INTMASK_SBE_SHIFT                  (13)
#define DWMCI_INTMASK_SBE_MASK                   (0x1 << DWMCI_INTMASK_SBE_SHIFT)
#define DWMCI_INTMASK_HLE_SHIFT                  (12)
#define DWMCI_INTMASK_HLE_MASK                   (0x1 << DWMCI_INTMASK_HLE_SHIFT)
#define DWMCI_INTMASK_FRUN_SHIFT                 (11)
#define DWMCI_INTMASK_FRUN_MASK                  (0x1 << DWMCI_INTMASK_FRUN_SHIFT)
#define DWMCI_INTMASK_HTO_SHIFT                  (10)
#define DWMCI_INTMASK_HTO_MASK                   (0x1 << DWMCI_INTMASK_HTO_SHIFT)
#define DWMCI_INTMASK_DRTO_SHIFT                 (9)
#define DWMCI_INTMASK_DRTO_MASK                  (0x1 << DWMCI_INTMASK_DRTO_SHIFT)
#define DWMCI_INTMASK_RTO_SHIFT                  (8)
#define DWMCI_INTMASK_RTO_MASK                   (0x1 << DWMCI_INTMASK_RTO_SHIFT)
#define DWMCI_INTMASK_DCRC_SHIFT                 (7)
#define DWMCI_INTMASK_DCRC_MASK                  (0x1 << DWMCI_INTMASK_DCRC_SHIFT)
#define DWMCI_INTMASK_RCRC_SHIFT                 (6)
#define DWMCI_INTMASK_RCRC_MASK                  (0x1 << DWMCI_INTMASK_RCRC_SHIFT)
#define DWMCI_INTMASK_RXDR_SHIFT                 (5)
#define DWMCI_INTMASK_RXDR_MASK                  (0x1 << DWMCI_INTMASK_RXDR_SHIFT)
#define DWMCI_INTMASK_RXDR                       (0x1 << DWMCI_INTMASK_RXDR_SHIFT)
#define DWMCI_INTMASK_TXDR_SHIFT                 (4)
#define DWMCI_INTMASK_TXDR_MASK                  (0x1 << DWMCI_INTMASK_TXDR_SHIFT)
#define DWMCI_INTMASK_TXDR                       (0x1 << DWMCI_INTMASK_TXDR_SHIFT)
#define DWMCI_INTMASK_DTO_SHIFT                  (3)
#define DWMCI_INTMASK_DTO_MASK                   (0x1 << DWMCI_INTMASK_DTO_SHIFT)
#define DWMCI_INTMASK_CMDD_SHIFT                 (2)
#define DWMCI_INTMASK_CMDD_MASK                  (0x1 << DWMCI_INTMASK_CMDD_SHIFT)
#define DWMCI_INTMASK_RE_SHIFT                   (1)
#define DWMCI_INTMASK_RE_MASK                    (0x1 << DWMCI_INTMASK_RE_SHIFT)
#define DWMCI_INTMASK_CD_SHIFT                   (0)
#define DWMCI_INTMASK_CD_MASK                    (0x1 << DWMCI_INTMASK_CD_SHIFT)
#define DWMCI_INTMASK_INT_SHIFT                  (0)
#define DWMCI_INTMASK_INT_MASK                   (0xFFFF << DWMCI_INTMASK_INT_SHIFT)
#define DWMCI_INTMASK_DATA_ERR                   (DWMCI_INTMASK_EBE_MASK | DWMCI_INTMASK_SBE_MASK | \
                                                  DWMCI_INTMASK_HLE_MASK | DWMCI_INTMASK_FRUN_MASK | \
                                                  DWMCI_INTMASK_EBE_MASK | DWMCI_INTMASK_DCRC_MASK)
#define DWMCI_INTMASK_DATA_TOUT                  (DWMCI_INTMASK_HTO_MASK | DWMCI_INTMASK_DRTO_MASK)

/* DWMCI_CMDARG */
#define DWMCI_CMDARG_SHIFT                       (0)
#define DWMCI_CMDARG_MASK                        (0xFFFFFFFF << DWMCI_CMDARG_SHIFT)

/* DWMCI_CMD */
#define DWMCI_CMD_START_CMD_SHIFT                (31)
#define DWMCI_CMD_START_CMD_MASK                 (0x1 << DWMCI_CMD_START_CMD_SHIFT)
#define DWMCI_CMD_START_CMD                      (0x1 << DWMCI_CMD_START_CMD_SHIFT)
#define DWMCI_CMD_USE_HOLD_REG_SHIFT             (29)
#define DWMCI_CMD_USE_HOLD_REG_MASK              (0x1 << DWMCI_CMD_USE_HOLD_REG_SHIFT)
#define DWMCI_CMD_USE_HOLD_REG                   (0x1 << DWMCI_CMD_USE_HOLD_REG_SHIFT)
#define DWMCI_CMD_VOLT_SWITCH_SHIFT              (28)
#define DWMCI_CMD_VOLT_SWITCH_MASK               (0x1 << DWMCI_CMD_VOLT_SWITCH_SHIFT)
#define DWMCI_CMD_BOOT_MODE_SHIFT                (27)
#define DWMCI_CMD_BOOT_MODE_MASK                 (0x1 << DWMCI_CMD_BOOT_MODE_SHIFT)
#define DWMCI_CMD_DISABLE_BOOT_SHIFT             (26)
#define DWMCI_CMD_DISABLE_BOOT_MASK              (0x1 << DWMCI_CMD_DISABLE_BOOT_SHIFT)
#define DWMCI_CMD_EXPECT_BOOT_ACK_SHIFT          (25)
#define DWMCI_CMD_EXPECT_BOOT_ACK_MASK           (0x1 << DWMCI_CMD_EXPECT_BOOT_ACK_SHIFT)
#define DWMCI_CMD_ENABLE_BOOT_SHIFT              (24)
#define DWMCI_CMD_ENABLE_BOOT_MASK               (0x1 << DWMCI_CMD_ENABLE_BOOT_SHIFT)
#define DWMCI_CMD_CCS_EXPECTED_SHIFT             (23)
#define DWMCI_CMD_CCS_EXPECTED_MASK              (0x1 << DWMCI_CMD_CCS_EXPECTED_SHIFT)
#define DWMCI_CMD_READ_CEATA_DEVICE_SHIFT        (22)
#define DWMCI_CMD_READ_CEATA_DEVICE_MASK         (0x1 << DWMCI_CMD_READ_CEATA_DEVICE_SHIFT)
#define DWMCI_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT   (21)
#define DWMCI_CMD_UPDATE_CLOCK_REGS_ONLY_MASK    (0x1 << DWMCI_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT)
#define DWMCI_CMD_UPDATE_CLOCK_REGS_ONLY         (0x1 << DWMCI_CMD_UPDATE_CLOCK_REGS_ONLY_SHIFT)
#define DWMCI_CMD_SEND_INITIALIZATION_SHIFT      (15)
#define DWMCI_CMD_SEND_INITIALIZATION_MASK       (0x1 << DWMCI_CMD_SEND_INITIALIZATION_SHIFT)
#define DWMCI_CMD_STOP_ABORT_CMD_SHIFT           (14)
#define DWMCI_CMD_STOP_ABORT_CMD_MASK            (0x1 << DWMCI_CMD_STOP_ABORT_CMD_SHIFT)
#define DWMCI_CMD_STOP_ABORT_CMD                 (0x1 << DWMCI_CMD_STOP_ABORT_CMD_SHIFT)
#define DWMCI_CMD_WAIT_PRVDATA_COMPLETE_SHIFT    (13)
#define DWMCI_CMD_WAIT_PRVDATA_COMPLETE_MASK     (0x1 << DWMCI_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)
#define DWMCI_CMD_WAIT_PRVDATA_COMPLETE          (0x1 << DWMCI_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)
#define DWMCI_CMD_SEND_AUTO_STOP_SHIFT           (12)
#define DWMCI_CMD_SEND_AUTO_STOP_MASK            (0x1 << DWMCI_CMD_SEND_AUTO_STOP_SHIFT)
#define DWMCI_CMD_TRANSFER_MODE_SHIFT            (11)
#define DWMCI_CMD_TRANSFER_MODE_MASK             (0x1 << DWMCI_CMD_TRANSFER_MODE_SHIFT)
#define DWMCI_CMD_WR_SHIFT                       (10)
#define DWMCI_CMD_WR_MASK                        (0x1 << DWMCI_CMD_WR_SHIFT)
#define DWMCI_CMD_WR                             (0x1 << DWMCI_CMD_WR_SHIFT)
#define DWMCI_CMD_DATA_EXPECTED_SHIFT            (9)
#define DWMCI_CMD_DATA_EXPECTED_MASK             (0x1 << DWMCI_CMD_DATA_EXPECTED_SHIFT)
#define DWMCI_CMD_DATA_EXPECTED                  (0x1 << DWMCI_CMD_DATA_EXPECTED_SHIFT)
#define DWMCI_CMD_CHECK_RESPONSE_CRC_SHIFT       (8)
#define DWMCI_CMD_CHECK_RESPONSE_CRC_MASK        (0x1 << DWMCI_CMD_CHECK_RESPONSE_CRC_SHIFT)
#define DWMCI_CMD_CHECK_RESPONSE_CRC             (0x1 << DWMCI_CMD_CHECK_RESPONSE_CRC_SHIFT)
#define DWMCI_CMD_RESPONSE_LENGTH_SHIFT          (7)
#define DWMCI_CMD_RESPONSE_LENGTH_MASK           (0x1 << DWMCI_CMD_RESPONSE_LENGTH_SHIFT)
#define DWMCI_CMD_RESPONSE_LENGTH                (0x1 << DWMCI_CMD_RESPONSE_LENGTH_SHIFT)
#define DWMCI_CMD_RESPONSE_EXPECT_SHIFT          (6)
#define DWMCI_CMD_RESPONSE_EXPECT_MASK           (0x1 << DWMCI_CMD_RESPONSE_EXPECT_SHIFT)
#define DWMCI_CMD_RESPONSE_EXPECT                (0x1 << DWMCI_CMD_RESPONSE_EXPECT_SHIFT)
#define DWMCI_CMD_CMD_INDEX_SHIFT                (5)
#define DWMCI_CMD_CMD_INDEX_MASK                 (0x3F << DWMCI_CMD_CMD_INDEX_SHIFT)

/* DWMCI_RESP0 */
#define DWMCI_RESP0_SHIFT                        (0)
#define DWMCI_RESP0_MASK                         (0xFFFFFFFF << DWMCI_RESP0_SHIFT)

/* DWMCI_RESP1 */
#define DWMCI_RESP1_SHIFT                        (0)
#define DWMCI_RESP1_MASK                         (0xFFFFFFFF << DWMCI_RESP1_SHIFT)

/* DWMCI_RESP2 */
#define DWMCI_RESP2_SHIFT                        (0)
#define DWMCI_RESP2_MASK                         (0xFFFFFFFF << DWMCI_RESP2_SHIFT)

/* DWMCI_RESP3 */
#define DWMCI_RESP3_SHIFT                        (0)
#define DWMCI_RESP3_MASK                         (0xFFFFFFFF << DWMCI_RESP3_SHIFT)

/* DWMCI_MINTSTS */
#define DWMCI_MINTSTS_SDIO_INTERRUPT_SHIFT       (24)
#define DWMCI_MINTSTS_SDIO_INTERRUPT_MASK        (0x1 << DWMCI_MINTSTS_SDIO_INTERRUPT_SHIFT)
#define DWMCI_MINTSTS_DATA_NOBUSY_SHIFT          (16)
#define DWMCI_MINTSTS_DATA_NOBUSY_MASK           (0x1 << DWMCI_MINTSTS_DATA_NOBUSY_SHIFT)
#define DWMCI_MINTSTS_EBE_SHIFT                  (15)
#define DWMCI_MINTSTS_EBE_MASK                   (0x1 << DWMCI_MINTSTS_EBE_SHIFT)
#define DWMCI_MINTSTS_ACD_SHIFT                  (14)
#define DWMCI_MINTSTS_ACD_MASK                   (0x1 << DWMCI_MINTSTS_ACD_SHIFT)
#define DWMCI_MINTSTS_SBE_SHIFT                  (13)
#define DWMCI_MINTSTS_SBE_MASK                   (0x1 << DWMCI_MINTSTS_SBE_SHIFT)
#define DWMCI_MINTSTS_HLE_SHIFT                  (12)
#define DWMCI_MINTSTS_HLE_MASK                   (0x1 << DWMCI_MINTSTS_HLE_SHIFT)
#define DWMCI_MINTSTS_FRUN_SHIFT                 (11)
#define DWMCI_MINTSTS_FRUN_MASK                  (0x1 << DWMCI_MINTSTS_FRUN_SHIFT)
#define DWMCI_MINTSTS_HTO_SHIFT                  (10)
#define DWMCI_MINTSTS_HTO_MASK                   (0x1 << DWMCI_MINTSTS_HTO_SHIFT)
#define DWMCI_MINTSTS_DRTO_SHIFT                 (9)
#define DWMCI_MINTSTS_DRTO_MASK                  (0x1 << DWMCI_MINTSTS_DRTO_SHIFT)
#define DWMCI_MINTSTS_RTO_SHIFT                  (8)
#define DWMCI_MINTSTS_RTO_MASK                   (0x1 << DWMCI_MINTSTS_RTO_SHIFT)
#define DWMCI_MINTSTS_DCRC_SHIFT                 (7)
#define DWMCI_MINTSTS_DCRC_MASK                  (0x1 << DWMCI_MINTSTS_DCRC_SHIFT)
#define DWMCI_MINTSTS_RCRC_SHIFT                 (6)
#define DWMCI_MINTSTS_RCRC_MASK                  (0x1 << DWMCI_MINTSTS_RCRC_SHIFT)
#define DWMCI_MINTSTS_RXDR_SHIFT                 (5)
#define DWMCI_MINTSTS_RXDR_MASK                  (0x1 << DWMCI_MINTSTS_RXDR_SHIFT)
#define DWMCI_MINTSTS_TXDR_SHIFT                 (4)
#define DWMCI_MINTSTS_TXDR_MASK                  (0x1 << DWMCI_MINTSTS_TXDR_SHIFT)
#define DWMCI_MINTSTS_DTO_SHIFT                  (3)
#define DWMCI_MINTSTS_DTO_MASK                   (0x1 << DWMCI_MINTSTS_DTO_SHIFT)
#define DWMCI_MINTSTS_CMDD_SHIFT                 (2)
#define DWMCI_MINTSTS_CMDD_MASK                  (0x1 << DWMCI_MINTSTS_CMDD_SHIFT)
#define DWMCI_MINTSTS_RE_SHIFT                   (1)
#define DWMCI_MINTSTS_RE_MASK                    (0x1 << DWMCI_MINTSTS_RE_SHIFT)
#define DWMCI_MINTSTS_CD_SHIFT                   (0)
#define DWMCI_MINTSTS_CD_MASK                    (0x1 << DWMCI_MINTSTS_CD_SHIFT)
#define DWMCI_MINTSTS_INT_STATUS_SHIFT           (0)
#define DWMCI_MINTSTS_INT_STATUS_MASK            (0xFFFF << DWMCI_MINTSTS_INT_STATUS_SHIFT)

/* DWMCI_RINTSTS */
#define DWMCI_RINTSTS_SDIO_INTERRUPT_SHIFT       (24)
#define DWMCI_RINTSTS_SDIO_INTERRUPT_MASK        (0x1 << DWMCI_RINTSTS_SDIO_INTERRUPT_SHIFT)
#define DWMCI_RINTSTS_SDIO_INTERRUPT             (0x1 << DWMCI_RINTSTS_SDIO_INTERRUPT_SHIFT)
#define DWMCI_RINTSTS_DATA_NOBUSY_SHIFT          (16)
#define DWMCI_RINTSTS_DATA_NOBUSY_MASK           (0x1 << DWMCI_RINTSTS_DATA_NOBUSY_SHIFT)
#define DWMCI_RINTSTS_EBE_SHIFT                  (15)
#define DWMCI_RINTSTS_EBE_MASK                   (0x1 << DWMCI_RINTSTS_EBE_SHIFT)
#define DWMCI_RINTSTS_ACD_SHIFT                  (14)
#define DWMCI_RINTSTS_ACD_MASK                   (0x1 << DWMCI_RINTSTS_ACD_SHIFT)
#define DWMCI_RINTSTS_SBE_SHIFT                  (13)
#define DWMCI_RINTSTS_SBE_MASK                   (0x1 << DWMCI_RINTSTS_SBE_SHIFT)
#define DWMCI_RINTSTS_HLE_SHIFT                  (12)
#define DWMCI_RINTSTS_HLE_MASK                   (0x1 << DWMCI_RINTSTS_HLE_SHIFT)
#define DWMCI_RINTSTS_FRUN_SHIFT                 (11)
#define DWMCI_RINTSTS_FRUN_MASK                  (0x1 << DWMCI_RINTSTS_FRUN_SHIFT)
#define DWMCI_RINTSTS_HTO_SHIFT                  (10)
#define DWMCI_RINTSTS_HTO_MASK                   (0x1 << DWMCI_RINTSTS_HTO_SHIFT)
#define DWMCI_RINTSTS_DRTO_SHIFT                 (9)
#define DWMCI_RINTSTS_DRTO_MASK                  (0x1 << DWMCI_RINTSTS_DRTO_SHIFT)
#define DWMCI_RINTSTS_RTO_SHIFT                  (8)
#define DWMCI_RINTSTS_RTO_MASK                   (0x1 << DWMCI_RINTSTS_RTO_SHIFT)
#define DWMCI_RINTSTS_DCRC_SHIFT                 (7)
#define DWMCI_RINTSTS_DCRC_MASK                  (0x1 << DWMCI_RINTSTS_DCRC_SHIFT)
#define DWMCI_RINTSTS_RCRC_SHIFT                 (6)
#define DWMCI_RINTSTS_RCRC_MASK                  (0x1 << DWMCI_RINTSTS_RCRC_SHIFT)
#define DWMCI_RINTSTS_RXDR_SHIFT                 (5)
#define DWMCI_RINTSTS_RXDR_MASK                  (0x1 << DWMCI_RINTSTS_RXDR_SHIFT)
#define DWMCI_RINTSTS_TXDR_SHIFT                 (4)
#define DWMCI_RINTSTS_TXDR_MASK                  (0x1 << DWMCI_RINTSTS_TXDR_SHIFT)
#define DWMCI_RINTSTS_DTO_SHIFT                  (3)
#define DWMCI_RINTSTS_DTO_MASK                   (0x1 << DWMCI_RINTSTS_DTO_SHIFT)
#define DWMCI_RINTSTS_CMDD_SHIFT                 (2)
#define DWMCI_RINTSTS_CMDD_MASK                  (0x1 << DWMCI_RINTSTS_CMDD_SHIFT)
#define DWMCI_RINTSTS_RE_SHIFT                   (1)
#define DWMCI_RINTSTS_RE_MASK                    (0x1 << DWMCI_RINTSTS_RE_SHIFT)
#define DWMCI_RINTSTS_CD_SHIFT                   (0)
#define DWMCI_RINTSTS_CD_MASK                    (0x1 << DWMCI_RINTSTS_CD_SHIFT)
#define DWMCI_RINTSTS_INT_STATUS_SHIFT           (0)
#define DWMCI_RINTSTS_INT_STATUS_MASK            (0xFFFF << DWMCI_RINTSTS_INT_STATUS_SHIFT)
#define DWMCI_RINTSTS_INT_STATUS                 (0xFFFF << DWMCI_RINTSTS_INT_STATUS_SHIFT)
#define DWMCI_RINTSTS_ALL                        (0xFFFFFFFF)

/* DWMCI_STATUS */
#define DWMCI_STATUS_DMA_REQ_SHIFT               (31)
#define DWMCI_STATUS_DMA_REQ_MASK                (0x1 << DWMCI_STATUS_DMA_REQ_SHIFT)
#define DWMCI_STATUS_DMA_ACK_SHIFT               (30)
#define DWMCI_STATUS_DMA_ACK_MASK                (0x1 << DWMCI_STATUS_DMA_ACK_SHIFT)
#define DWMCI_STATUS_FIFO_COUNT_SHIFT            (17)
#define DWMCI_STATUS_FIFO_COUNT_MASK             (0x1FFF << DWMCI_STATUS_FIFO_COUNT_SHIFT)
#define DWMCI_STATUS_RESPONSE_INDEX_SHIFT        (11)
#define DWMCI_STATUS_RESPONSE_INDEX_MASK         (0x3F << DWMCI_STATUS_RESPONSE_INDEX_SHIFT)
#define DWMCI_STATUS_DATA_STATE_MC_BUSY_SHIFT    (10)
#define DWMCI_STATUS_DATA_STATE_MC_BUSY_MASK     (0x1 << DWMCI_STATUS_DATA_STATE_MC_BUSY_SHIFT)
#define DWMCI_STATUS_DATA_BUSY_SHIFT             (9)
#define DWMCI_STATUS_DATA_BUSY_MASK              (0x1 << DWMCI_STATUS_DATA_BUSY_SHIFT)
#define DWMCI_STATUS_DATA_3_STATUS_SHIFT         (8)
#define DWMCI_STATUS_DATA_3_STATUS_MASK          (0x1 << DWMCI_STATUS_DATA_3_STATUS_SHIFT)
#define DWMCI_STATUS_COMMAND_FSM_STATES_SHIFT    (4)
#define DWMCI_STATUS_COMMAND_FSM_STATES_MASK     (0xF << DWMCI_STATUS_COMMAND_FSM_STATES_SHIFT)
#define DWMCI_STATUS_FIFO_FULL_SHIFT             (3)
#define DWMCI_STATUS_FIFO_FULL_MASK              (0x1 << DWMCI_STATUS_FIFO_FULL_SHIFT)
#define DWMCI_STATUS_FIFO_EMPTY_SHIFT            (2)
#define DWMCI_STATUS_FIFO_EMPTY_MASK             (0x1 << DWMCI_STATUS_FIFO_EMPTY_SHIFT)
#define DWMCI_STATUS_FIFO_TX_WATERMARK_SHIFT     (1)
#define DWMCI_STATUS_FIFO_TX_WATERMARK_MASK      (0x1 << DWMCI_STATUS_FIFO_TX_WATERMARK_SHIFT)
#define DWMCI_STATUS_FIFO_RX_WATERMARK_SHIFT     (0)
#define DWMCI_STATUS_FIFO_RX_WATERMARK_MASK      (0x1 << DWMCI_STATUS_FIFO_RX_WATERMARK_SHIFT)

/* DWMCI_FIFOTH */
#define DWMCI_FIFOTH_MSIZE_SHIFT                 (28)
#define DWMCI_FIFOTH_MSIZE_MASK                  (0x7 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_1                     (0x0 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_4                     (0x1 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_8                     (0x2 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_16                    (0x3 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_32                    (0x4 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_64                    (0x5 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_128                   (0x6 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_MSIZE_256                   (0x7 << DWMCI_FIFOTH_MSIZE_SHIFT)
#define DWMCI_FIFOTH_RX_WMARK_SHIFT              (16)
#define DWMCI_FIFOTH_RX_WMARK_MASK               (0xFFF << DWMCI_FIFOTH_RX_WMARK_SHIFT)
#define DWMCI_FIFOTH_TX_WMARK_SHIFT              (0)
#define DWMCI_FIFOTH_TX_WMARK_MASK               (0xFFF << DWMCI_FIFOTH_TX_WMARK_SHIFT)

#define DWMCI_RX_WMARK(x)                        ((x) << DWMCI_FIFOTH_RX_WMARK_SHIFT)
#define DWMCI_TX_WMARK(x)                        ((x) << DWMCI_FIFOTH_TX_WMARK_SHIFT)

/* DWMCI_CDETECT */
#define DWMCI_CDETECT_SHIFT                      (0)
#define DWMCI_CDETECT_MASK                       (0x1 << DWMCI_CDETECT_SHIFT)

/* DWMCI_WRTPRT */
#define DWMCI_WRTPRT_WRITE_PROTECT_SHIFT         (0)
#define DWMCI_WRTPRT_WRITE_PROTECT_MASK          (0x1 << DWMCI_WRTPRT_WRITE_PROTECT_SHIFT)

/* DWMCI_TCBCNT */
#define DWMCI_TCBCNT_SHIFT                       (0)
#define DWMCI_TCBCNT_MASK                        (0xFFFFFFFF << DWMCI_TCBCNT_SHIFT)

/* DWMCI_TBBCNT */
#define DWMCI_TBBCNT_SHIFT                       (0)
#define DWMCI_TBBCNT_MASK                        (0xFFFFFFFF << DWMCI_TBBCNT_SHIFT)

/* DWMCI_DEBNCE */
#define DWMCI_DEBNCE_SHIFT                       (0)
#define DWMCI_DEBNCE_MASK                        (0xFFFFFF << DWMCI_DEBNCE_SHIFT)

/* DWMCI_USRID 0x07967797 */
#define DWMCI_USRID_SHIFT                        (0)
#define DWMCI_USRID_MASK                         (0xFFFFFFFF << DWMCI_USRID_SHIFT)

/* DWMCI_VERID 0x5342270a */
#define DWMCI_VERID_SHIFT                        (0)
#define DWMCI_VERID_MASK                         (0xFFFFFFFF << DWMCI_VERID_SHIFT)

/* DWMCI_HCON */
#define DWMCI_HCON_NUM_CLK_DIVIDER_SHIFT         (24)
#define DWMCI_HCON_NUM_CLK_DIVIDER_MASK          (0x3 << DWMCI_HCON_NUM_CLK_DIVIDER_SHIFT)
#define DWMCI_HCON_SET_CLK_FALSE_PATH_SHIFT      (23)
#define DWMCI_HCON_SET_CLK_FALSE_PATH_MASK       (0x1 << DWMCI_HCON_SET_CLK_FALSE_PATH_SHIFT)
#define DWMCI_HCON_IMPLEMENT_HOLD_REG_SHIFT      (22)
#define DWMCI_HCON_IMPLEMENT_HOLD_REG_MASK       (0x1 << DWMCI_HCON_IMPLEMENT_HOLD_REG_SHIFT)
#define DWMCI_HCON_IMPLEMENT_HOLD_REG_NOHOLD_REG (0x0 << DWMCI_HCON_IMPLEMENT_HOLD_REG_SHIFT)
#define DWMCI_HCON_IMPLEMENT_HOLD_REG_HOLD_REG   (0x1 << DWMCI_HCON_IMPLEMENT_HOLD_REG_SHIFT)
#define DWMCI_HCON_FIFO_RAM_INSIDE_SHIFT         (21)
#define DWMCI_HCON_FIFO_RAM_INSIDE_MASK          (0x1 << DWMCI_HCON_FIFO_RAM_INSIDE_SHIFT)
#define DWMCI_HCON_FIFO_RAM_INSIDE_outside       (0x0 << DWMCI_HCON_FIFO_RAM_INSIDE_SHIFT)
#define DWMCI_HCON_FIFO_RAM_INSIDE_inside        (0x1 << DWMCI_HCON_FIFO_RAM_INSIDE_SHIFT)
#define DWMCI_HCON_GE_DMA_DATA_WIDTH_SHIFT       (18)
#define DWMCI_HCON_GE_DMA_DATA_WIDTH_MASK        (0x7 << DWMCI_HCON_GE_DMA_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_GE_DMA_DATA_WIDTH_16          (0x0 << DWMCI_HCON_GE_DMA_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_GE_DMA_DATA_WIDTH_32          (0x1 << DWMCI_HCON_GE_DMA_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_GE_DMA_DATA_WIDTH_64          (0x2 << DWMCI_HCON_GE_DMA_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_DMA_INTERFACE_SHIFT           (16)
#define DWMCI_HCON_DMA_INTERFACE_MASK            (0x3 << DWMCI_HCON_DMA_INTERFACE_SHIFT)
#define DWMCI_HCON_DMA_INTERFACE_NONE            (0x0 << DWMCI_HCON_DMA_INTERFACE_SHIFT)
#define DWMCI_HCON_DMA_INTERFACE_DW_DMA          (0x1 << DWMCI_HCON_DMA_INTERFACE_SHIFT)
#define DWMCI_HCON_DMA_INTERFACE_GENERIC_DMA     (0x2 << DWMCI_HCON_DMA_INTERFACE_SHIFT)
#define DWMCI_HCON_DMA_INTERFACE_NON_DW_DMA      (0x3 << DWMCI_HCON_DMA_INTERFACE_SHIFT)
#define DWMCI_HCON_H_ADDR_WIDTH_SHIFT            (10)
#define DWMCI_HCON_H_ADDR_WIDTH_MASK             (0x3F << DWMCI_HCON_H_ADDR_WIDTH_SHIFT)
#define DWMCI_HCON_H_ADDR_WIDTH(n)               ((n-1) << DWMCI_HCON_H_DATA_WIDTH_SHIFT) /* 8-32 */
#define DWMCI_HCON_H_DATA_WIDTH_SHIFT            (7)
#define DWMCI_HCON_H_DATA_WIDTH_MASK             (0x7 << DWMCI_HCON_H_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_H_DATA_WIDTH_16               (0x0 << DWMCI_HCON_H_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_H_DATA_WIDTH_32               (0x1 << DWMCI_HCON_H_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_H_DATA_WIDTH_64               (0x2 << DWMCI_HCON_H_DATA_WIDTH_SHIFT)
#define DWMCI_HCON_H_BUS_TYPE_SHIFT              (6)
#define DWMCI_HCON_H_BUS_TYPE_MASK               (0x1 << DWMCI_HCON_H_BUS_TYPE_SHIFT)
#define DWMCI_HCON_H_BUS_TYPE_APB                (0x0 << DWMCI_HCON_H_BUS_TYPE_SHIFT)
#define DWMCI_HCON_H_BUS_TYPE_AHB                (0x1 << DWMCI_HCON_H_BUS_TYPE_SHIFT)
#define DWMCI_HCON_NUM_CARDS_SHIFT               (1)
#define DWMCI_HCON_NUM_CARDS_MASK                (0x1F << DWMCI_HCON_NUM_CARDS_SHIFT)
#define DWMCI_HCON_CARD_TYPE_SHIFT               (0)
#define DWMCI_HCON_CARD_TYPE_MASK                (0x1 << DWMCI_HCON_CARD_TYPE_SHIFT)
#define DWMCI_HCON_CARD_TYPE_MMC_ONLY            (0x0 << DWMCI_HCON_CARD_TYPE_SHIFT)
#define DWMCI_HCON_CARD_TYPE_SD_MMC              (0x1 << DWMCI_HCON_CARD_TYPE_SHIFT)

#define DWMCI_GET_TRANS_MODE(x)                  (((x) & DWMCI_HCON_DMA_INTERFACE_MASK) >> DWMCI_HCON_DMA_INTERFACE_SHIFT)

#define DWMCI_IDMAC_OWN                          (1 << 31)
#define DWMCI_IDMAC_CH                           (1 << 4)
#define DWMCI_IDMAC_FS                           (1 << 3)
#define DWMCI_IDMAC_LD                           (1 << 2)

/* DWMCI_UHS_REG */
#define DWMCI_UHS_REG_SHIFT                      (16)
#define DWMCI_UHS_REG_MASK                       (0x1 << DWMCI_UHS_REG_SHIFT)

/* DWMCI_RSTN */
#define DWMCI_RSTN_SHIFT                         (0)
#define DWMCI_RSTN_MASK                          (0x1 << DWMCI_RSTN_SHIFT)

/* DWMCI_BMOD */
#define DWMCI_BMOD_PBL_SHIFT                     (8)
#define DWMCI_BMOD_PBL_MASK                      (0x7 << DWMCI_BMOD_PBL_SHIFT)
#define DWMCI_BMOD_DE_SHIFT                      (7)
#define DWMCI_BMOD_DE_MASK                       (0x1 << DWMCI_BMOD_DE_SHIFT)
#define DWMCI_BMOD_DE                            (0x1 << DWMCI_BMOD_DE_SHIFT)
#define DWMCI_BMOD_DSL_SHIFT                     (2)
#define DWMCI_BMOD_DSL_MASK                      (0x1 << DWMCI_BMOD_DSL_SHIFT)
#define DWMCI_BMOD_FB_SHIFT                      (1)
#define DWMCI_BMOD_FB_MASK                       (0x1 << DWMCI_BMOD_FB_SHIFT)
#define DWMCI_BMOD_FB                            (0x1 << DWMCI_BMOD_FB_SHIFT)
#define DWMCI_BMOD_SWR_SHIFT                     (0)
#define DWMCI_BMOD_SWR_MASK                      (0x1 << DWMCI_BMOD_SWR_SHIFT)
#define DWMCI_BMOD_SWR                           (0x1 << DWMCI_BMOD_SWR_SHIFT)

/* DWMCI_PLDMND */
#define DWMCI_PLDMND_SHIFT                       (0)
#define DWMCI_PLDMND_MASK                        (0xFFFFFFFF << DWMCI_PLDMND_SHIFT)

/* DWMCI_DBADDR */
#define DWMCI_DBADDR_SHIFT                       (0)
#define DWMCI_DBADDR_MASK                        (0xFFFFFFFF << DWMCI_DBADDR_SHIFT)

/* DWMCI_IDSTS */
#define DWMCI_IDSTS_FSM_SHIFT                    (13)
#define DWMCI_IDSTS_FSM_MASK                     (0xF << DWMCI_IDSTS_FSM_SHIFT)
#define DWMCI_IDSTS_EB_SHIFT                     (10)
#define DWMCI_IDSTS_EB_MASK                      (0x7 << DWMCI_IDSTS_EB_SHIFT)
#define DWMCI_IDSTS_RW_SHIFT                     (9)
#define DWMCI_IDSTS_RW_MASK                      (0x1 << DWMCI_IDSTS_RW_SHIFT)
#define DWMCI_IDSTS_NIS_SHIFT                    (8)
#define DWMCI_IDSTS_NIS_MASK                     (0x1 << DWMCI_IDSTS_NIS_SHIFT)
#define DWMCI_IDSTS_CES_SHIFT                    (5)
#define DWMCI_IDSTS_CES_MASK                     (0x1 << DWMCI_IDSTS_CES_SHIFT)
#define DWMCI_IDSTS_DU_SHIFT                     (4)
#define DWMCI_IDSTS_DU_MASK                      (0x1 << DWMCI_IDSTS_DU_SHIFT)
#define DWMCI_IDSTS_FBE_SHIFT                    (2)
#define DWMCI_IDSTS_FBE_MASK                     (0x1 << DWMCI_IDSTS_FBE_SHIFT)
#define DWMCI_IDSTS_RI_SHIFT                     (1)
#define DWMCI_IDSTS_RI_MASK                      (0x1 << DWMCI_IDSTS_RI_SHIFT)
#define DWMCI_IDSTS_TI_SHIFT                     (0)
#define DWMCI_IDSTS_TI_MASK                      (0x1 << DWMCI_IDSTS_TI_SHIFT)

/* DWMCI_IDINTEN */
#define DWMCI_IDINTEN_AI_SHIFT                   (9)
#define DWMCI_IDINTEN_AI_MASK                    (0x1 << DWMCI_IDINTEN_AI_SHIFT)
#define DWMCI_IDINTEN_NI_SHIFT                   (8)
#define DWMCI_IDINTEN_NI_MASK                    (0x1 << DWMCI_IDINTEN_NI_SHIFT)
#define DWMCI_IDINTEN_CES_SHIFT                  (5)
#define DWMCI_IDINTEN_CES_MASK                   (0x1 << DWMCI_IDINTEN_CES_SHIFT)
#define DWMCI_IDINTEN_DU_SHIFT                   (4)
#define DWMCI_IDINTEN_DU_MASK                    (0x1 << DWMCI_IDINTEN_DU_SHIFT)
#define DWMCI_IDINTEN_FBE_SHIFT                  (2)
#define DWMCI_IDINTEN_FBE_MASK                   (0x1 << DWMCI_IDINTEN_FBE_SHIFT)
#define DWMCI_IDINTEN_RI_SHIFT                   (1)
#define DWMCI_IDINTEN_RI_MASK                    (0x1 << DWMCI_IDINTEN_RI_SHIFT)
#define DWMCI_IDINTEN_TI_SHIFT                   (0)
#define DWMCI_IDINTEN_TI_MASK                    (0x1 << DWMCI_IDINTEN_TI_SHIFT)

/* DWMCI_DSCADDR */
#define DWMCI_DSCADDR_SHIFT                      (0)
#define DWMCI_DSCADDR_MASK                       (0xFFFFFFFF << DWMCI_DSCADDR_SHIFT)

/* DWMCI_BUFADDR */
#define DWMCI_BUFADDR_SHIFT                      (0)
#define DWMCI_BUFADDR_MASK                       (0xFFFFFFFF << DWMCI_BUFADDR_SHIFT)

/* DWMCI_CARDTHRCTL */
#define DWMCI_CARDTHRCTL_CARDRDTHRESHOLD_SHIFT   (16)
#define DWMCI_CARDTHRCTL_CARDRDTHRESHOLD_MASK    (0xFFF << DWMCI_CARDTHRCTL_CARDRDTHRESHOLD_SHIFT)
#define DWMCI_CARDTHRCTL_BSYCLRINTEN_SHIFT       (1)
#define DWMCI_CARDTHRCTL_BSYCLRINTEN_MASK        (0x1 << DWMCI_CARDTHRCTL_BSYCLRINTEN_SHIFT)
#define DWMCI_CARDTHRCTL_CARDRDTHREN_SHIFT       (0)
#define DWMCI_CARDTHRCTL_CARDRDTHREN_MASK        (0x1 << DWMCI_CARDTHRCTL_CARDRDTHREN_SHIFT)

/* DWMCI_BACK_END_POWER */
#define DWMCI_BACK_END_POWER_SHIFT               (0)
#define DWMCI_BACK_END_POWER_MASK                (0x1 << DWMCI_BACK_END_POWER_SHIFT)

/* DWMCI_EMMC_DDR_REG */
#define DWMCI_EMMC_DDR_REG_SHIFT                 (0)
#define DWMCI_EMMC_DDR_REG_MASK                  (0x1 << DWMCI_EMMC_DDR_REG_SHIFT)

/* DWMCI_FIFO_BASE */
#define DWMCI_FIFO_BASE_SHIFT                    (0)
#define DWMCI_FIFO_BASE_MASK                     (0xFFFFFFFF << DWMCI_FIFO_BASE_SHIFT)

#endif /* __ROCKCHIP_DWMCI_H__ */
